Second generation 5G platform architecture
CEVA has introduced PentaG2, its second generation 5G platform architecture aimed at accelerating the proliferation of new usage models for mobile broadband and IoT, and to reduce the entry barriers for handset OEMs looking to internalise 5G modem design.
PentaG2 is a comprehensive hardware/software IP platform that combines advanced DSPs with special purpose accelerators for optimal signal chain processing, to deliver a 4X improvement in power efficiency versus its predecessor.
The recent Ericsson Mobility Report forecasts that cellular IoT will comprise 5.5 billion of the overall 8.9 billion cellular connections in 2027, up from 1.9 billion cellular IoT connections in 2021. Furthermore, the number of fixed wireless access (FWA) connections is expected to grow from 90 million in 2021 to reach almost 230 million in 2027. PentaG2 substantially lowers the high entry barriers for semiconductor companies and OEMs who wish to address these huge market opportunities in mobile broadband and IoT, or to be self-sufficient in the 5G handset SoC, by providing a comprehensive platform with the key building blocks required for full LTE/5G modem design.
PentaG2 platforms will initially be offered in the following configurations:
• PentaG2-Max – targeting eMBB use cases in handsets and CPE/FWA Terminals and mmWave, NR-Sidelink and cellular V2X (C-V2X), as well as URLLC enabled AR/VR use cases. PentaG2-Max is the world’s only complete IP offering able to efficiently process the immense workloads required for 3GPP releases 16 and 17, looking forward to 5G advanced, for both Sub-6 and mmWave 5G broadband, with a 4X performance/area improvement in data-path processing.
• PentaG2-Lite – supports a range of reduced capacity use cases, including LTE Cat1 and future 3GPP Rel-17/18 NR RedCap (Reduced Capacity, aka NR-Lite). PentaG2-Lite is an extremely efficient and lean baseband implementation with complete processing chain acceleration and utilizing a small footprint DSP controller, to meet the most stringent power budgets.
Both configurations offer the flexibility to allow customers combine their own proprietary algorithms and IP, such as channel estimation or advanced equalisation with the PentaG2 platform via standard interfaces.
Guy Keshet, Vice President and General Manager of the Mobile Broadband Business Unit at CEVA, said: “While 5G today is predominantly associated with smartphones, it offers an immense opportunity to expand the use of cellular technology to new markets that are not fully utilising the potential of 5G, including industrial, robotics, wearables, healthcare, automotive, fixed wireless access and smart grid. These new verticals open the door to semiconductor companies and OEMs to develop application-specific 5G modems in-house rather than relying on traditional, costly cellular modems from incumbent cellular vendors. PentaG2 bridges the design gap to develop a 5G modem by providing the full baseband processing platform in a cost and power efficient solution, which can also be leveraged by handset OEMs looking to internalize their 5G modem design.”
The PentaG2 platform architecture builds on the success of the first-generation platform, which has shipped in millions of 5G NR smartphones and mobile broadband devices to date. PentaG2 includes a complete set of programmable accelerators and coprocessors, constituting end-to-end in-line signal processing chains. Accelerators introduced for the first time as part of the PentaG2 platform include:
• Bit Demodulation Unit, supporting entire Rx bit and LLR processing
• Bit Modulation Unit for entire Tx bit processing
• Equalizer and MAC engine co-processor Unit
• 5G LDPC Encoder / Decoder, and
• 5G Polar Encoder / Decoder
Other hardware accelerators include HARQ, MLD, Multi-radix DFT, Turbo FEC and Viterbi FEC, and a neural network coprocessor for 5G link adaptation. All accelerators come with standard AXI interfaces for ease of integration. The platform also includes a scalar DSP for PHY control, hardware acceleration scheduling, and running the protocol stack. The PentaG2-Max also features a vector DSP with 5G ISA extensions for handling workloads required for channel estimation.
The PentaG2 platform also provides a complete L1 SW functional implementation of all 5G processing chains, running on the control DSP and utilizing all the platform’s hardware accelerators, including PDSCH, PUSCH, PDCCH and PUCCH.
To further simplify and accelerate development, PentaG2 deliverables include an advanced platform System-C simulation environment that allows system engineers, architects and software developers to model, profile and debug their designs, pre-silicon. This simulator supports all PentaG2 components and interfaces seamlessly with MATLAB for algorithmic development. The whole PentaG2 system can be emulated on a FPGA platform for further verification.